EC-Crypto: Highly Efficient Area-Delay Optimized Elliptic Curve Cryptography Processor

Elliptic Curve Cryptography (ECC) based security protocols require much shorter key space which makes ECC the most suitable option for resource-limited devices as compared to other public cryptography (PKC) schemes. This paper presents a highly efficient area-delay optimized crypto processor over general prime field ( $\mathbb {F}_{p}$ ). It is structured on new novel finite multiplier (FFM) where several optimization techniques have been incorporated shorten latency and hardware resource consumption. The proposed FFM architecture embedded with adder/subtractor (FFAS) unit utilized perform FFAS operations instead of deploying dedicated unit. Common Z (Co-Z) coordinates Montgomery ladder method are used compute point multiplication, core operation in all ECC-based protocols. work also proposes an scheduling strategy execute low-level arithmetic primitives minimum employed units. Due these techniques, resources, latency, throughput. captured Verilog-HDL, synthesized, implemented Virtex-7, Kintex-7, Virtex-6 FPGA platforms using Xilinx Vivado ISE Design Suite tools. On Virtex-7 platform, it computes single 256-bit scalar multiplication primitive notation="LaTeX">$0.7~m\text{s}$ , consumes just 6.2K slices, delivers throughput 1428 per second. implementation results show that design outperforming state-of-the-art by providing better product higher efficiency. Therefore, has potential be deployed many applications both requirements critical.